11.3 Interfacing with LVDS Display

The SAMA7D65 SOM Series includes one 4-Lane Low-Voltage Differential Signaling (LVDS). The LVDS operates at low power and can run at very high speeds by only using twisted-pair interfaces.

The LVDS Controller manages data format conversion from the LCD Controller’s internal DPI bus to OpenLDI LVDS output signals. LVDS Controller’s functions include bit mapping, balanced mode management and serialization.

Table 11-6. LVDS Interface Configurations
Interface Instance	Power Rail	Pin No.	GPIO Name	Pin Name	Description
LVDS	VDDLVDS	9	PE4	LVDS_D0_N	Differential LVDS Data Line 0 Transceiver Output
LVDS	VDDLVDS	10	PE5	LVDS_D0_P	Differential LVDS Data Line 0 Transceiver Output
LVDS	VDDLVDS	12	PE6	LVDS_D1_N	Differential LVDS Data Line 1 Transceiver Output
LVDS	VDDLVDS	13	PE7	LVDS_D1_P	Differential LVDS Data Line 1 Transceiver Output
LVDS	VDDLVDS	15	PE8	LVDS_D2_N	Differential LVDS Data Line 2 Transceiver Output
LVDS	VDDLVDS	16	PE9	LVDS_D2_P	Differential LVDS Data Line 2 Transceiver Output
LVDS	VDDLVDS	19	PE10	LVDS_D3_N	Differential LVDS Data Line 3 Transceiver Output
LVDS	VDDLVDS	20	PE11	LVDS_D3_P	Differential LVDS Data Line 3 Transceiver Output
LVDS	VDDLVDS	17	PE12	LVDS_CLK_N	Differential LVDS Clock Line Transceiver Output
LVDS	VDDLVDS	18	PE13	LVDS_CLK_P	Differential LVDS Clock Line Transceiver Output

Note: For the use of the LVDS features, the VDDLVDS input power must be connected to the VDD_2V5 output volltage.