Pin Allocation Tables

Table . 28-Pin Allocation Table
I/O(2) 28-Pin SPDIP, SOIC, SSOP 28-Pin (V)QFN A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-up Basic

RA0

2

27

ANA0

C1IN0-

C2IN0-

IOCA0

Y

RA1

3

28

ANA1

C1IN1-

C2IN1-

IOCA1

Y

RA2

4

1

ANA2

DAC1OUT1

VREF- (DAC)

VREF- (ADC)

C1IN0+

C2IN0+

IOCA2

Y

RA3

5

2

ANA3

VREF+ (DAC)

VREF+ (ADC)

C1IN1+

IOCA3

MDCARL(1)

Y

RA4

6

3

ANA4

T0CKI(1)

IOCA4

MDCARH(1)

Y

RA5

7

4

ANA5

IOCA5

MDSRC(1)

SS1(1)

Y

RA6

10

7

ANA6

IOCA6

Y

CLKOUT

OSC2

RA7

9

6

ANA7

IOCA7

Y

OSC1

CLKIN

RB0

21

18

ANB0

C2IN1+

CWG1(1)

ZCDIN

IOCB0

INT0(1)

SS2(1)

Y
RB1 22 19 ANB1 C1IN3-

C2IN3-

IOCB1

INT1(1)

SCK2(1)

SCL2(3,4)

Y
RB2 23 20 ANB2 IOCB2

INT2(1)

SDI2(1)

SDA2(3,4)

Y
RB3 24 21 ANB3 C1IN2-

C2IN2-

IOCB3 Y
RB4 25 22 ANB4 T5G(1) IOCB4 Y
RB5 26 23 ANB5 T1G(1) IOCB5 Y
RB6 27 24 ANB6 IOCB6 CK2(1,3) Y ICSPCLK
RB7 28 25 ANB7 DAC1OUT2 T6IN(1) IOCB7 RX2/DT2(1,3) Y ICSPDAT
RC0 11 8 ANC0 T1CKI(1)

T3CKI(1)

T3G(1)

IOCC0 Y SOSCO
RC1 12 9 ANC1 CCP2(1) IOCC1 Y SOSCIN

SOSCI

RC2 13 10 ANC2 T5CKI(1) CCP1(1) IOCC2 Y
RC3 14 11 ANC3 T2IN(1) IOCC3 SCK1(1)

SCL1(3,4)

Y
RC4 15 12 ANC4 IOCC4 SDI1(1)

SDA1(3,4)

Y
RC5 16 13 ANC5 T4IN(1) IOCC5 Y
RC6 17 14 ANC6 IOCC6 CK1(1,3) Y
RC7 18 15 ANC7 IOCC7 RX1/DT1(1,3) Y
RE3 1 26 IOCE3 Y Vpp/MCLR
VSS 19 16 VSS
VDD(5) 20 17 VDD
VSS 8 5 VSS
OUT(2) ADGRDA

ADGRDB

C1OUT

C2OUT

TMR0 CCP1

CCP2

PWM3

PWM4

CWG1A

CWG1B

CWG1C

CWG1D

TX1/CK1(3)

DT1(3)

TX2/CK2(3)

DT2(3)

DSM SDO1

SCK1

SDO2

SCK2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which port pins may be used for this signal.
  2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table.
  3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
  4. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
  5. A 0.1 μF bypass capacitor to VSS is required on the VDD pin.
Table . 40/44-Pin Allocation Table
I/O(2) 40-Pin PDIP 40-Pin QFN 44-Pin TQFP A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-up Basic

RA0

2

17

19

ANA0

C1INO-

C2IN0-

IOCA0

Y

RA1

3

18

20

ANA1

C1IN1-

C2IN1-

IOCA1

Y

RA2

4

19

21

ANA2

DAC1OUT1

VREF- (DAC5)

VREF- (ADC)

C1IN0+

C2IN0+

IOCA2

Y

RA3

5

20

22

ANA3

VREF+ (DAC5)

VREF+ (ADC)

C1IN1+

IOCA3

MDCARL(1)

Y

RA4

6

21

23

ANA4

T0CKI(1)

IOCA4

MDCARH(1)

Y

RA5

7

22

24

ANA5

IOCA5

MDSRC(1)

SS1(1)

Y

RA6

14

29

31

ANA6

IOCA6

Y

CLKOUT

OSC2

RA7

13

28

30

ANA7

IOCA7

Y

OSC1

CLKIN

RB0

33

8

8

ANB0

C2IN1+

CWG1(1)

ZCDIN

IOCB0

INT0(1)

SS2(1)

Y

RB1

34

9

9

ANB1

C1IN3-

C2IN3-

IOCB1

INT1(1)

SCK2(1)

SCL2(3,4)

Y

RB2

35

10

10

ANB2

IOCB2

INT2(1)

SDI2(1)

SDA2(3,4)

Y

RB3

36

11

11

ANB3

C1IN2-

C2IN2-

IOCB3

Y

RB4

37

12

14

ANB4

T5G(1)

IOCB4

Y

RB5

38

13

15

ANB5

T1G(1)

IOCB5

Y

RB6

39

14

16

ANB6

IOCB6

CK2(1,3)

Y

ICSPCLK

RB7

40

15

17

ANB7

DAC1OUT2

T6IN(1)

IOCB7

RX2/DT2(1,3)

Y

ICSPDAT

RC0

15

30

32

ANC0

T1CKI(1)

T3CKI(1)

T3G(1)

IOCC0

Y

SOSCO

RC1

16

31

35

ANC1

CCP2(1)

IOCC1

Y

SOSCIN

SOSCI

RC2

17

32

36

ANC2

T5CKI(1)

CCP1(1)

IOCC2

Y

RC3

18

33

37

ANC3

T2IN(1)

IOCC3

SCK1(1)

SCL1(3,4)

Y

RC4

23

38

42

ANC4

IOCC4

SDI1(1)

SDA1(3,4)

Y

RC5

24

39

43

ANC5

T4IN(1)

IOCC5

Y

RC6

25

40

44

ANC6

IOCC6

CK1(1,3)

Y

RC7

26

1

1

ANC7

IOCC7

RX1/DT1(1,3)

Y

RD0

19

34

38

AND0

Y

RD1

20

35

39

AND1

Y

RD2

21

36

40

AND2

Y

RD3

22

37

41

AND3

Y

RD4

27

2

2

AND4

Y

RD5

28

3

3

AND5

Y

RD6

29

4

4

AND6

Y

RD7

30

5

5

AND7

Y

RE0

8

23

25

ANE0

Y

RE1

9

24

26

ANE1

Y

RE2

10

25

27

ANE2

Y

RE3

1

16

18

IOCE3

Y

Vpp/MCLR

VSS

12

6

6

VSS

VDD(5)

11

7

7

VDD

VDD(5)

32

26

28

VSS

VSS

31

27

29

VSS

OUT(2)

ADGRDA

ADGRDB

C1OUT

C2OUT

TMR0

CCP1

CCP2

PWM3

PWM4

CWG1A

CWG1B

CWG1C

CWG1D

TX1/CK1(3)

DT1(3)

TX2/CK2(3)

DT2(3)

DSM SDO1

SCK1

SDO2

SCK2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which port pins may be used for this signal.
  2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table.
  3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
  4. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
  5. A 0.1 μF bypass capacitor to VSS is required on all VDD pins.