Digital Peripherals

  • Configurable Logic Cell (CLC):
    • Integrated combinational and sequential logic
  • Complementary Waveform Generator (CWG):
    • Rising and falling edge dead-band control
    • Full-bridge, half-bridge, 1-channel drive
    • Multiple signal sources
  • Capture/Compare/PWM (CCP) modules:
    • Two CCPs
    • 16-bit resolution for Capture/Compare modes
    • 10-bit resolution for PWM mode
  • 10-Bit Pulse-Width Modulators (PWM):
    • Two 10-bit PWMs
  • Serial Communications:
    • Two Enhanced USART (EUSART) with Auto-Baud Detect, Auto-wake-up on Start, 
RS-232, RS-485, LIN compatible
    • SPI
    • I2C, SMBus and PMBus™ compatible
  • Up to 35 I/O Pins and One Input Pin:
    • Individually programmable pull-ups
    • Slew rate control
    • Interrupt-on-change on all pins
    • Input level selection control
  • Programmable CRC with Memory Scan:
    • Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B)
    • Calculate CRC over any portion of Flash or EEPROM
    • High-speed or background operation
  • Hardware Limit Timer (TMR2/4/6+HLT):
    • Hardware monitoring and Fault detection
  • Peripheral Pin Select (PPS):
    • Enables pin mapping of digital I/O
  • Data Signal Modulator (DSM)