Core Features

  • C Compiler Optimized RISC Architecture
  • Operating Speed:
    • DC – 64 MHz clock input over the full VDD range
    • 62.5 ns minimum instruction cycle
  • Programmable 2-Level Interrupt Priority
  • 31-Level Deep Hardware Stack
  • Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT)
  • Four 16-Bit Timers (TMR0/1/3/5)
  • Low-Current Power-on Reset (POR)
  • Power-up Timer (PWRT)
  • Brown-out Reset (BOR)
  • Low-Power BOR (LPBOR) Option
  • Windowed Watchdog Timer (WWDT):
    • Watchdog Reset on too long or too short interval between watchdog clear events
    • Variable prescaler selection
    • Variable window size selection
    • All sources configurable in hardware or software