Table 34-1. Op Amp Summary Table| Op Amp Module Instances | Clock Input | Peripheral Bus Speed |
|---|
| 3 | None | Slow (1:4 CPU Clock) |
Table 34-2. Op Amp Availability by Device Package| Package | Op Amp Availability |
|---|
| 64-Pin | OA1, OA2, OA3 |
| 48-Pin | OA1, OA2, OA3 |
| 36-Pin | OA1, OA2 |
Table 34-3. Op Amp Calibration Register
Description| Name | Address | Bit Field | Bit 28/20/12/4 | Bit 24/16/8/0 |
|---|
| FOPAMPHP | 0x007F2100 | 31:24 | — | — |
| 23:16 | NTRIM3 | PTRIM3 |
| 15:8 | NTRIM2 | PTRIM2 |
| 7:0 | NTRIM1 | PTRIM1 |
| FOPAMPLP | 0x007F20F0 | 31:24 | — | — |
| 23:16 | NTRIM3 | PTRIM3 |
| 15:8 | NTRIM2 | PTRIM2 |
| 7:0 | NTRIM1 | PTRIM1 |
Note: The calibration registers FOPAMPLP and FOPAMPHP are placed at
0x007F20F0 and 0x007F2100, respectively. These registers can be read to determine the
factory-calibrated trim settings.
