16.5 16-bit Resolution Mode

Though the ADC SAR core is 12-bit, the resolution of the ADC can be increased to 16-bit using an oversampling technique. The ADC can accumulate 256 measurements, which provides an additional 4 bits to the resolution. The 16-bit mode is enabled when both the MODE bits and ACCNUM bits in the ADxCHyCON register are set to three (oversampling of 256 samples option). The 16-bit result is available in the ADxCHyDATA register. When all 256 conversions are accumulated and the result is in the ADxCHyDATA register, the CHyRDY bit is set in the ADxSTAT register. This CHyRDY flag is cleared by hardware when the ADxCHyDATA register is read. The interrupt mode selection bit IRQSEL in the ADxCHyCON register must be set (= ‘1’) to detect when the 16-bit data in the ADxCHyDATA register is ready using a channel interrupt (ADxCHyIF bit in the corresponding IFS register). When the ADC operates at the maximum conversion speed (40 MSPS), the 16-bit mode allows converting at 40MSPS/256 = 156 kSPS. The maximum 16-bit result conversion rate of 156 kSPS is achieved when the ADC module is clocked from 320 MHz and the sampling time is set to a minimum (0.5TAD, SAMC bits in the ADxCHyCON register are zero).