23.4.18 I2C Host Input Delay Compensation Register
Note:
- Default value is 0x0012 (18 x I2C UPB clock time), where the assumed UPB clock is 50 MHz, and the path delay is 360 ns with 2.3V and 1.1K pull-up resistance (worst case).
| Name: | I2CxHDLYC |
| Offset: | 0x18CC, 0x191C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| HIDLYCEN | |||||||||
| Access | R/W | ||||||||
| Reset | 1 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HIDLYC[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HIDLYC[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | x | x | x | x | x | x | x | x | |
Bit 31 – HIDLYCEN I2C Host Input Delay Compensation Enable bit
| Value | Description |
|---|---|
| 1 | Programmable hardware host input delay compensation is enabled (default). |
| 0 | Fixed hardware host input delay compensation is used. |