5.3 Power Management Unit

The SAM9X60D1G-I/LZB System-On-Module is supplied by an external supply (5V_MAIN) and generates its own internal supplies via the Microchip MCP16501 power management unit.

The MCP16501 is a full-featured Power Management Integrated Circuit (PMIC), cost and size optimized for Microchip MPU devices such as the SAM9X60D1G.

The MCP16501 integrates three DC-DC buck regulators used for system supplying and one auxiliary LDO for customer purposes.
  • All buck channels can support loads up to 1A. All bucks are 100% duty cycle capable.
    • DCDC1 set to 3.3 V supplies all pads of the embedded devices. This power rail offers a 600-mA load to customer application through pins 41 and 42 (VDD_3V3).
    • DCDC2 set to 1.8V supplies the DDR2 memory. This power rail offers a 600-mA load to customer application through pins 54 and 55 (VDDIOM).
    • DCDC3 set to 1.15V supplies the microprocessor core.
  • One 300-mA LDO is provided so that sensitive analog loads can be supported.

The default power channel sequencing is built-in, as required by the Microchip SAM9X60D1G MPU device.

Active discharge resistors are provided on each output. All buck channels support safe start-up into pre-biased outputs.

The MCP16501 is available in a 4x4 mm 24-pin VQFN package.

The LPM pin of the Microchip SAM9X60 SOM, combined with the PWRHLD (also named SHDN) status pin of the MCP16501 PMIC, define different power states, which are illustrated in the table below.

PWRHLD LPM Buck1 Buck2 Buck3 LDO1 nRST Power State (1)
0 0 Off Off Off LEN Controlled Low Off
0 1 Off On(2) Off LEN Controlled Low Hibernate mode
1 1 On(2) On(2) On(2) LEN Controlled HiZ Low-Power mode
1 0 On(3) On(3) On(3) LEN Controlled HiZ Active mode

For more information about the PMIC MCP16501, see Reference Documents.

Note:

  1. Only allowed modes are listed. If the PWRHLD/LPM combination is not listed, the mode is not allowed.

  2. In this mode, the DCDC is configured in Automatic Pulse-Frequency Modulation (Auto-PFM) mode.

  3. In this mode, the DCDC is configured in Force Pulse-Width Modulation (FPWM) mode.

For more information about the use of the MCP16501 PMIC LPM feature, refer to the MCP16501 data sheet (see Reference Documents).

The LPM pin is controlled externally, as shown in the figure below.

Figure 5-4. LPM Schematic