48.9.3 Sleep Mode Current Consumption

Sleep mode configuration and measurements are defined in this section.

Remember: In Sleep mode, power consumption of the device is optimized with respect to response time.
  • VDD3V3 = 3.3V
  • VDDCORE/VDDPLL = Internal Voltage regulator used
  • TA = 25°C
  • Core clock (CPU_CLK0) stopped
  • Sub-system main clocks (MCK0, MCK0DIV,MCK0DIV2), running at various frequencies from PLLs.
  • All peripheral clocks deactivated
  • No activity on I/O lines
  • Current measurement as illustrated in the figure below
Figure 48-29. Measurement Setup for Sleep Mode
Table 48-56. Typical Sleep Mode Current Consumption Versus Frequency
Core Clock / Main Clock (MHz)AMP1AMP2Unit
Core Clock/Main Clock MCK0, MCK0DIV, MCK0DIV2
200/200, 100, 2002119mA
100/100, 100, 1001312mA
50/50, 50, 5098mA