The flowcharts shown in this section provide examples for read and
write operations. A polling or interrupt method can be used to check the status bits. The
interrupt method requires that the Interrupt Enable register (FLEX_TWI_IER) be configured
first.
Figure 33-99. TWI Write Operation with Single Data Byte without Internal
AddressFigure 33-100. TWI Write Operation with Single Data Byte and Internal
AddressFigure 33-101. TWI Write Operation with Multiple Data Bytes with or without
Internal AddressFigure 33-102. SMBus Write Operation with Multiple Data Bytes with or
without Internal Address and PEC SendingFigure 33-103. SMBus Write Operation with Multiple Data Bytes with PEC and
Alternative Command ModeFigure 33-104. TWI Write Operation with Multiple Data Bytes and Read
Operation with Multiple Data Bytes (Sr)Figure 33-105. TWI Write Operation with Multiple Data Bytes + Read Operation
and Alternative Command Mode + PECFigure 33-106. TWI Read Operation with Single Data Byte without Internal
AddressFigure 33-107. TWI Read Operation with Single Data Byte and Internal
AddressFigure 33-108. TWI Read Operation with Multiple Data Bytes with or without
Internal AddressFigure 33-109. TWI Read Operation with Multiple Data Bytes with or without
Internal Address with PECFigure 33-110. TWI Read Operation with Multiple Data Bytes with Alternative
Command Mode with PECFigure 33-111. TWI Read Operation with Multiple Data Bytes + Write Operation
with Multiple Data Bytes (Sr)Figure 33-112. TWI Read Operation with Multiple Data Bytes + Write with
Alternative Command Mode with PEC
DS60001780C
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