16.4.5 Managing Resets at Application Level

If a reset source is enabled, it acts on the systems as described in the table below. See the corresponding peripheral sections for further details on resets.

• VDD3V3 Supply Monitor reset – Full system reset.
• VDDCORE Supply Monitor reset – Full system reset.
• 32.768 kHz Crystal Oscillator Failure Detection reset – Full system reset except the second peripheral set.
• CPU Clock Failure Detection reset – Full system reset.
• Watchdog 0 reset – Full system reset except the second peripheral set. The reset of the PMC can be configured with RSTC_MR.WDTPMC0. The second peripheral set must be managed by RSTC_MR.CPEREN.
• Watchdog 1 reset – Full system reset except the second peripheral set. The reset of the PMC can be configured with RSTC_MR.WDTPMC1. The second peripheral set must be managed by RSTC_MR.CPEREN.
• Software reset – Full system reset except the second peripheral set. The reset of the PMC can be configured with RSTC_MR.SFTPMCRS. The second peripheral set must be managed by RSTC_MR.CPEREN
• User reset (NRST pin) – Full system reset. To avoid this, the User reset must be configured to generate an interrupt and not a reset (RSTC_MR.URSTEN = 0 and RSTC_MR.URSTIEN = 1).