20.4.3 PMD Control Register 2
| Name: | PMD2 |
| Offset: | 0x010E |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLC3MD | CLC2MD | CLC1MD | PMW2MD | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 7 – CLC3MD Disable CLC3
| Value | Description |
|---|---|
| 1 | CLC3 disabled |
| 0 | CLC3 enabled |
Bit 6 – CLC2MD Disable CLC2
| Value | Description |
|---|---|
| 1 | CLC2 disabled |
| 0 | CLC2 enabled |
Bit 5 – CLC1MD Disable CLC1
| Value | Description |
|---|---|
| 1 | CLC1 disabled |
| 0 | CLC1 enabled |
Bit 0 – PMW2MD Disable PWM2
| Value | Description |
|---|---|
| 1 | PWM2 module disabled |
| 0 | PWM2 module enabled |