5.4 Software Features and Enhancements

If a CCC External Feedback Delay goes outside the FPGA, you can add the set_external_delay SDC timing constraint to specify the delay of the external feedback path to the PLL. You can add, update, or delete set_external_delay constraints from the Editor in Constraint Manager. For more information about this constraint, see the topic SmartTime Tcl Commands in the Tcl Commands Reference Guide .

The timing report will include the feedback delay in the Clock generation step of the expanded path.

Users can export an interrupt map report for Soft Mi-V-based designs. This report file represents the entire connection hierarchy of the Mi-V processor interrupt pins. For more information, see the topic Exporting Interrupt Map Report in the Tcl Commands Reference Guide .

The Timing Report Explorer in Libero SoC v2023.1 adds a path range option for Slack Distribution, Logic Level Distribution, Cell/Net Delay Pie, and Data charts. See the topic Slack Distribution in the Libero SoC Design Flow User Guide .

Libero SoC v2023.1 now supports JTAG programming and debug chains involving Microchip devices from ProASIC3, IGLOO, and SmartFusion families as well as non-Microchip devices. During chain programming, ProASIC 3, IGLOO,ProASIC3 nano, IGLOO nano, IGLOO Plus, and SmartFusion devices will be treated as bypass devices. In addition, VJTAG voltage levels across boards in a chain must be equal; otherwise, an error is generated. Integrated SmartDebug supports Post-Route Probe Insertion when devices are connected in a chain.

The Synplify Pro and Identify tools bundled in Libero SoC v2023.1 have been upgraded to SynplifyPro T-2022.09M-SP2 and Identify Debugger T-2022.09M-SP2 versions. Key enhancements are:

Starting with v2023.1, Libero SoC is supported on the Ubuntu 22.04.1 LTS operating system.

For a complete list of supported operating systems, see section Supported Operating Systems.

The PolarFire® SoC Microprocessor Subsystem (MSS) Configurator documentation is also available as a part of the Libero SoC Design Suite Help Documentation webhelp. The webhelp features a very flexible layout and is designed to adapt to any screen size to provide an optimal viewing and interaction experience. Each topic and subtopic have an (Ask a Question) link that allows you to get answers to technical questions or to report inaccurate or incomplete information while viewing the help documentation. You can also use this link to file a technical support case with Microchip Technical Support.

• Click here to visit the new Libero SoC Design Suite Help Documentation WebHelp online.
• Click here to download a copy of the latest Libero SoC Design Suite Help documentation (in HTML file format) for offline reference. Extract the contents of the .zip archive and open index.html in a web browser of choice.