1.1.2 Logic Modules

Microchip's Axcelerator family provides two types of logic modules: The register cell (R-cell) and the combinatorial cell (C-cell). The Axcelerator device can implement more than 4,000 combinatorial functions of up to five inputs (see the following figure).

Figure 1-3. AX C-Cell and R-Cell

The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and active-low enable control signals (see the preceeding figure). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility (for example, easy mapping of dual-data-rate functions into the FPGA), while conserving valuable clock resources. The clock source for the R-cell can be chosen from the hardwired clocks, routed clocks, or internal logic.

Two C-cells, a single R-cell, two Transmit (TX), and two Receive (RX) routing buffers form a Cluster, while two Clusters comprise a SuperCluster (see the following figure). Each SuperCluster also contains an independent Buffer (B) module, which supports buffer insertion on high-fanout nets by the place-and-route tool, minimizing system delays while improving logic utilization.

Figure 1-4. AX SuperCluster

The logic modules within the SuperCluster are arranged so that two combinatorial modules are side by side, giving a C–C–R – C–C–R pattern to the SuperCluster. This C–C–R pattern enables efficient implementation (minimum delay) of two-bit carry logic for improved arithmetic performance (see the following figure).

Figure 1-5. AX 2-Bit Carry Logic

The AX architecture is fully fracturable, meaning that if one or more of the logic modules in a SuperCluster are used by a particular signal path, the other logic modules are still available for use by other paths.

At the chip level, SuperClusters are organized into core tiles, which are arrayed to build up the full chip. For example, the AX1000 is composed of a 3x3 array of nine core tiles. The array of core tiles is surrounded by blocks of I/O Clusters and the I/O bank ring (see the following table). Each core tile consists of an array of 336 SuperClusters and four SRAM blocks (176 SuperClusters and three SRAM blocks for the AX250).

The following table shows the number of core tiles per device.

Table 1-1. Number of Core Tiles per Device
Device	Number of Core Tiles
AX125	1 regular tile
AX250	4 smaller tiles
AX500	4 regular tiles
AX1000	9 regular tiles
AX2000	16 regular tiles

The SRAM blocks are arranged in a column on the west side of the tile (see the following figure).

Figure 1-6. AX Device Architecture (AX1000 shown)