Table 47-12. Operating
Conditions(1)
Symbol |
Parameters |
Conditions |
Min |
Typ |
Max |
Unit |
RES |
Input resolution |
|
- |
- |
10 |
Bits |
VDDANA |
Analog supply voltage |
|
2.7 |
- |
5.5 |
V |
AVREF |
External reference voltage |
|
1 |
- |
VDDANA - 0.6 |
V |
INTREF |
VREF.SEL = 0x0 |
- |
1.024 |
- |
V |
VREF.SEL = 0x2 |
- |
2.048 |
- |
VREF.SEL = 0x3 |
- |
4.096 (2) |
- |
VDDANA |
|
- |
VDDANA |
- |
V |
|
Linear output voltage range |
|
0.05 |
- |
VDDANA - 0.05 |
V |
|
Minimum resistive load |
|
5 |
- |
- |
kΩ |
|
Maximum capacitance load |
|
- |
- |
100 |
pF |
- These are based on simulation. These values are not covered by test or
characterization.
- For VDDANA > 4.5V.
Table 47-13. Clock and Timing(1)
Symbol |
Parameter |
Conditions |
Max. |
Units |
|
Conversion rate |
Cload=100pF Rload >
5kΩ |
Normal
mode |
350 |
ksps |
For
DDATA=±1 |
1000 |
|
Startup
time |
|
|
3 |
μs |
1. These values are based on simulation.
These values are not covered by test limits in production or characterization.
Table 47-14. Accuracy Characteristics(1)
Symbol |
Parameter |
Conditions |
Typ. |
Max. |
Units |
INL |
Integral non-linearity |
VREF= Ext 2.0V |
VDD = 2.7V |
+/-0.7 |
+/-2.4 |
LSB |
VDD = 5.5V |
+/-0.5 |
+/-1.6 |
VREF = VDDANA |
VDD = 2.7V |
+/-0.6 |
+/-2.0 |
VDD = 5.5V |
+/-0.4 |
+/-1.6 |
VREF= 1.024V INTREF |
VDD = 2.7V |
+/-1.0 |
+/-2.5 |
VDD = 5.5V |
+/-1.5 |
+/-3.5 |
DNL |
Differential non-linearity |
VREF= Ext 2.0V |
VDD = 2.7V |
+/-0.3 |
+/-2.3 |
LSB |
VDD = 5.5V |
+/-0.4 |
+/-2.2 |
VREF = VDDANA |
VDD = 2.7V |
+/-0.2 |
+/-2.1 |
VDD = 5.5V |
+/-0.2 |
+/-2.1 |
VREF= 1.024V INTREF |
VDD = 2.7V |
+/-1.0 |
+/-2.5 |
VDD = 5.5V |
+/-1.4 |
+/-3.5 |
GE |
Gain error |
Ext. VREF |
|
+/-8 |
+/-28 |
mV |
OE |
Offset error |
Ext. VREF |
|
+/-4 |
+/-26 |
mV |
- These values are based on characterization. These values are not covered by test
limits in production.