45.12.3 Digital Phase Locked Loop (DPLL) Characteristics

Table 45-52. Fractional Digital Phase Locked Loop Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
fIN(1) Input frequency 32 2000 KHz
fOUT(1) DCO Output frequency 48 96 MHz
Jp(2)

Period jitter

(Peak-Peak value)

 fIN = 32 kHz, fOUT = 48 MHz - 1.5 3.0 %
fIN = 32 kHz, fOUT = 64 MHz - 1.7 4.0
fIN = 32 kHz, fOUT = 96 MHz - 2.7 8.0
fIN = 2 MHz, fOUT = 48 MHz - 1.8 4.0
fIN = 2 MHz, fOUT = 64 MHz - 1.9 4.0
fIN = 2 MHz, fOUT = 96 MHz - 2.5 6.0
tLOCK(2) Lock Time

After startup, time to get lock signal.

fIN = 32 kHz,

fOUT = 96 MHz

 - 1.1 1.5 ms

After startup, time to get lock signal.

fIN = 2 MHz,

fOUT = 96 MHz

 - 25 35 μs
Duty(1) Duty cycle - - 50 - %
  1. These values are based on simulation, and are not covered by test limits in production or characterization.
  2. These values are based on characterization.
  3. DPLL jitter is sensitive to digital on-chip activity, which is application dependent.
Table 45-53. Power Consumption(1)
Symbol Parameters Conditions Ta Typ. Max. Units
IDD Current Consumption Ck = 48 MHz, VDD = 5.0V

Max 85°C

Typ 25°C

 536 612 µA
Ck = 64 MHz, VDD = 5.0V 640 721
Ck = 96 MHz, VDD = 5.0V 865 970
  1. These values are based on characterization.