33.4.2.5 ADC Clock

The ADC clock (CLK_ADC) is derived by scaling down the APB clock (CLK_ADCn_APB). The amount of scaling is configured by the Prescaler bit field in the Control B register (CTRLB.PRESC). Refer to the ADC section of the Electrical Characteristics chapter for details on the minimum and maximum allowed values for ADC clock (CLK_ADC) period.

Some of the internal timings in the ADC are independent of CLK_ADC. The Timebase bit field in the Control B register (CTRLB.TIMEBASE) specifies the number of CLK_ADCn_APB cycles that is equivalent to or larger than 1 μs. This value is used for timing internal delays, such as ADC start-up times. The value must be rounded up to the nearest integer. The following code example shows how to do this using the ceil function.

#include <math.h>
#define CLK_ADCn_APB 24000000ul // 24 MHz
#define TIMEBASE_VALUE ((uint8_t) ceil(CLK_ADCn_APB*0.000001))