33.4.2.7 Conversion Timing

Some of the analog components in the ADC are disabled between conversions and require time to initialize before a conversion starts. Only the components used by the current ADC configuration are enabled, and since the initializations run in parallel, the limiting factor is the module with the slowest initialization time. The ADC Busy (ADCBUSY) bit in the Status (STATUS) register can be used to check if initialization is ongoing. Refer to the Electrical Characteristics chapter for the initialization times needed by the analog modules.

When the On Demand bit in the Control A register (CTRLA.ONDEMAND) is ‘0’, the latency of the ADC peripheral is reduced. This keeps the configured modules continuously enabled, effectively eliminating all initialization time at the start of a conversion. However, initialization time is still required when enabling the ADC for the first time and when reconfiguring the ADC to use an input or reference that requires initialization.

The sampling period of the ADC is configured using the Sample Length bit field in the Control E register (CTRLE.SAMPLEN), and is SAMPLEN + 1 CLK_ADC cycles.

Table 33-6. Conversion Timing
Mode	Resolution	Trigger Detection	Initialization	Sampling	Data Conversion	Result Update
Single-Ended	8	3 * CLK_ADCn_APB	t_INIT	(SAMPLEN + 1) * CLK_ADC	8	3 * CLK_ADCn_APB
	10				10
	12				12
	13				13
Differential	8				9
	10				11
	12				13
	13				13

Figure 33-3. Timing Diagram - Single Conversion

Figure 33-4. Timing Diagram - Series Accumulation

Figure 33-5. Timing Diagram - Burst Accumulation