22.4.2.6 Double Buffering

The Compare Channels (CC[n]) registers and the Period (PER) register are double buffered. Each buffer register has a buffer valid bit (CCBUFVn or PERBUFV) in the STATUS register, which indicates that the buffer register contains a new valid value that can be copied into the corresponding register. As long as the respective buffer valid status flags (PERBUFV or CCBUFVn) are set to ‘1’, the related Synchronization Busy bits (SYNCBUSY.PER or SYNCBUSY.CCn) are set (SYNCBUSY.PER or SYNCBUSY.CCn). A write to the respective PER/PERBUF or CC[n]/CCBUF[n] registers will generate a PAC error, and access to the respective PER or CC[n] register is invalid.

When the Buffer Valid Flag bit in the STATUS register is ‘1’, the data from buffer registers will be copied into the corresponding register under hardware UPDATE conditions. After the update the Buffer Valid Flag bits in the STATUS register are automatically cleared by hardware. This automatic update through hardware can be disabled by writing a ‘1’ to the Lock Update bit in the Control B Set register (CTRLBSET.LUPD).

Note: The software update command (CTRLBSET.CMD=0x3) is acting independently of the LUPD value and can force an update even if hardware updates are locked.

A compare register is double buffered, as in the following figure.

Figure 22-7. Compare Channel Double Buffering

Both the registers (PER/CC[n]) and the corresponding buffer registers (PERBUF/CCBUF[n]) are available in the I/O register map, and the double buffering feature is not mandatory. Double buffering is disabled by writing a ‘1’ to the Lock Update bit in the Control B Set register (CTRLBSET.LUPD).

Changing the Period

The counter period can be changed by writing a new TOP value to the Period register (PER or CC0, depending on the waveform generation and TC mode). Any TOP value update to the registers (PER or CC[n]) becomes effective only after the synchronization delay.

Figure 22-8. Unbuffered Single-Slope Up-Counting Operation

A counter wrap-around can occur in any operation mode when counting upwards without buffering, see Figure 22-8.

COUNT and TOP are continuously compared, so when a new TOP value that is lower than the current COUNT is written to TOP, COUNT will wrap before a compare match occurs.

Figure 22-9. Unbuffered Single-Slope Down-Counting Operation

When double buffering is used, the buffer register (PERBUF or CCBUF[n]) can be written at any time and the counter will still maintain correct operation. The period register (PER or CC[n]) is always updated on the update condition, as shown in Figure 22-10. This prevents wrap-around and the generation of odd waveforms.

Figure 22-10. Changing the Period Using Buffering