32.6.2 Sequential Control
Note: The SEQCTRL register is
enable-protected when CCL.CTRLA.ENABLE =
1.| Name: | SEQCTRL |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Local Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SEQSEL1[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SEQSEL0[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 0:3, 8:11 – SEQSELx Sequential Selection x
These bit fields select the sequential configuration:
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Sequential logic is disabled |
| 0x1 | DFF | D flip-flop |
| 0x2 | JK | JK flip-flop |
| 0x3 | LATCH | D latch |
| 0x4 | RS | RS latch |
| 0x5 - 0xF | — | Reserved |