32.6.1 Control A
Note: The RUNSTDBY bit in this register is
enable-protected when CCL.CTRLA.ENABLE =
1.| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | Local Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | ENABLE | SWRST | |||||||
| Access | R/W | R/W | W | ||||||
| Reset | 0 | 0 | 0 |
Bit 6 – RUNSTDBY Run in Standby
This bit indicates whether the GCLK_CCL clock must be kept running in Standby mode. This setting is ignored for configurations where the generic clock is not required. For details, refer to the Sleep Mode Operation section.
Important: This bit must be written before enabling the CCL.
| Value | Description |
|---|---|
| 0 | A generic clock is not required in Standby sleep mode |
| 1 | A generic clock is required in Standby sleep mode |
Bit 1 – ENABLE Enable
| Value | Description |
|---|---|
| 0 | The peripheral is disabled |
| 1 | The peripheral is enabled |
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the CCL
to their initial state.
| Value | Description |
|---|---|
| 0 | There is no reset operation in progress |
| 1 | The reset operation is in progress |