32.6.3 LUT Control n

Note: The LUTCTRL[n] register is enable-protected when CCL.CTRLA.ENABLE=1.
Name: LUTCTRL[n]
Offset: 0x08 + n*0x04 [n=0..3]
Reset: 0x00000000
Property: Local Write-Protection, Enable-Protected

Bit 3130292827262524 
 TRUTH[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
  LUTEOLUTEILUTINVINSEL2[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 15141312111098 
 INSEL1[3:0]INSEL0[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 EDGESEL FILTSEL[1:0]     
Access R/WR/WR/W 
Reset 000 

Bits 31:24 – TRUTH[7:0] Truth Table

This bit field defines the output value of the truth logic as a function of the inputs IN[2:0].

Bit 22 – LUTEO LUT Event Output Enable

ValueDescription
0 LUT event output is disabled
1 LUT event output is enabled

Bit 21 – LUTEI LUT Event Input Enable

ValueDescription
0 LUT incoming event is disabled
1 LUT incoming event is enabled

Bit 20 – LUTINV LUT Inverted Event Input Enable

ValueDescription
0 Incoming event is not inverted
1 Incoming event is inverted

Bits 8:11, 12:15, 16:19 – INSELn LUT Input n Source Selection

These bit fields select the source for LUT input n. Refer to Input Selection Multiplexer to see the specific input signals that can be connected.

ValueNameDescription
0x0 MASK Masked input
0x1 FEEDBACK Feedback input source
0x2 LINK Linked LUT input source
0x3 EVENT Event input source
0x4 IO I/O pin input source
0x5 AC AC input source
0x6 TC TC input source
0x8 TCC TCC input source
0x9 SERCOM SERCOM input source
0xB ASYNCEVENT Asynchronous event input source
Other Reserved

Bit 7 – EDGESEL Edge Selection

ValueDescription
0 Edge detector is disabled
1 Edge detector is enabled

Bits 5:4 – FILTSEL[1:0] Filter Selection

This bit field selects the LUT output filter options:

ValueNameDescription
0x0 DISABLE Filter disabled
0x1 SYNCH Synchronizer enabled
0x2 FILTER Filter enabled
0x3 Reserved