18.4.3.3.1 CoreSight Identification

A system-level Arm CoreSight ROM table is present in the device to identify the vendor and the chip identification method. Its address is provided in the MEM-AP BASE register inside the Arm Debug Access Port. The CoreSight ROM implements a 64-bit conceptual ID, composed as follows from the PID0 to PID7 CoreSight ROM Table registers:

Figure 18-3. Conceptual 64-bit Peripheral ID
Table 18-2. Conceptual 64-Bit Peripheral ID Bit Descriptions
FieldSizeDescriptionLocation
JEP-106 CC code4Microchip Continuation code: 0x0PID4
JEP-106 ID code7Microchip Device ID: 0x29PID1+PID2
4KB count4Indicates that the CoreSight component is a ROM: 0x0PID4
RevAnd4Not used; read as 0PID3
CUSMOD4Not used; read as 0PID3
PARTNUM12Contains 0xCD0 to indicate that DSU is presentPID0+PID1
REVISION4

DSU revision which starts at 0x0 and increments by 1 for each version of the DSU

PID2

For more information, refer to the Arm Debug Interface Version 5 Architecture Specification.