22.7.3 Control B Set

This register allows the user to change its content without performing a read-modify-write operation. Any changes made tp this register will also be reflected in the Control B Clear register (CTRLBCLR).

Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the that synchronization of the CTRLBCLR register is complete.

Name:	CTRLBSET
Offset:	0x05
Reset:	0x00
Property:	PAC Write-Protection, Read-Synchronized, Write-Synchronized


Bit	7	6	5	4	3	2	1	0
	CMD[2:0]					ONESHOT	LUPD	DIR
Access	R/W	R/W	R/W			R/W	R/W	R/W
Reset	0	0	0			0	0	0

Bits 7:5 – CMD[2:0] Command

This bit field is used for software control of the TC. Commands are executed on the next prescaled GCLK_TC clock cycle. When a command has been executed, the CMD bit field will be read back as zero.

Writing a 0x0 to this bit field has no effect.

Writing any value other than 0x0, as specified in the following table will issue a command for execution.

Important: This command requires synchronization before being executed. A valid sequence is:

Issue the CMD command (CTRLBSET.CMD = command)
Wait for CMD synchronization (SYNCBUSY.CTRLB = 0)
Wait for CMD bit field read back as zero (CTRLBSET.CMD = 0)

Value	Name	Description
0x0	NONE	No action
0x1	RETRIGGER	Force a start, restart or retrigger
0x2	STOP	Force a stop
0x3	UPDATE	Force update of double buffered registers
0x4	READSYNC	Force a read synchronization of COUNT
0x5	DMAOS	One-shot DMA trigger
Other	—	Reserved

Bit 2 – ONESHOT One-Shot on Counter

This bit controls one-shot operation of the TC.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will enable one-shot operation.

Value	Description
0	The TC will wrap around and continue counting when the next overflow or underflow condition
1	The TC will wrap around and stop on the next underflow or overflow condition

Bit 1 – LUPD Lock Update

This bit controls the update operation of the TC buffered registers.

When CTRLB.LUPD is set, the registers are not updated with the values from their buffered registers upon a hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before a hardware update is performed. After all buffer registers are loaded correctly, the buffered registers can be unlocked.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the LUPD bit.

This bit has no effect when the input capture operation is enabled.

Value	Description
0	The CCBUF[n] and PERBUF buffer registers values are copied into the CC[n] and PER registers upon hardware update condition
1	The CCBUF[n] and PERBUF buffer registers values are not copied into the CC[n] and PER registers upon hardware update condition

Bit 0 – DIR Counter Direction

This bit is used to change the direction of the counter.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the bit and cause the counter count down.

Value	Description
0	The timer/counter is counting up (incrementing)
1	The timer/counter is counting down (decrementing)