22.7.2 Control B Clear

This register allows the user to modify its contents without performing a read-modify-write operation. Any changes made to this register will also be reflected in the Control B Set register (CTRLBSET).

Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure that synchronization of the CTRLBCLR register is complete.

Name:	CTRLBCLR
Offset:	0x04
Reset:	0x00
Property:	PAC Write-Protection, Read-Synchronized, Write-Synchronized


Bit	7	6	5	4	3	2	1	0
	CMD[2:0]					ONESHOT	LUPD	DIR
Access	R/W	R/W	R/W			R/W	R/W	R/W
Reset	0	0	0			0	0	0

Bits 7:5 – CMD[2:0] Command

Writing 0x0 to this bit field has no effect.

Writing a value other than 0x0 to this bit field will clear the pending command. Refer CMD bit field in CTRLBSET register for commands.

Bit 2 – ONESHOT One-Shot on Counter

This bit controls one-shot operation of the TC.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will disable one-shot operation.

Value	Description
0	The TC will wrap around and continue counting when the next overflow or underflow condition occurs
1	The TC will wrap around and stop on the next underflow or overflow condition

Bit 1 – LUPD Lock Update

This bit controls the update operation of the TC buffered registers.

When CTRLB.LUPD is set, the registers are not updated with the values from their buffered registers upon a hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before a hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.

This bit has no effect when input capture operation is enabled.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the LUPD bit.

Value	Description
0	The CCBUF[n] and PERBUF buffer registers values are copied into the CC[n] and PER registers upon a hardware update condition
1	The CCBUF[n] and PERBUF buffer registers values are not copied into the CC[n] and PER registers upon a hardware update condition

Bit 0 – DIR Counter Direction

This bit is used to change the direction of the counter.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the bit and cause the counter count up.

Value	Description
0	The timer/counter is counting up (incrementing)
1	The timer/counter is counting down (decrementing)