22.7.1 Control A


Bit	31	30	29	28	27	26	25	24
				CAPTMODE1[1:0]			CAPTMODE0[1:0]
Access				R/W	R/W		R/W	R/W
Reset				0	0		0	0


Bit	23	22	21	20	19	18	17	16
			COPEN1	COPEN0			CAPTEN1	CAPTEN0
Access			R/W	R/W			R/W	R/W
Reset			0	0			0	0


Bit	15	14	13	12	11	10	9	8
	DMAOS				ALOCK	PRESCALER[2:0]
Access	R/W				R/W	R/W	R/W	R/W
Reset	0				0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ONDEMAND	RUNSTDBY	PRESCSYNC[1:0]		MODE[1:0]		ENABLE	SWRST
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	W
Reset	0	0	0	0	0	0	0	0

Bits 28:27 – CAPTMODE1[1:0] Capture mode Channel 1

This bit field selects the channel 1 capture mode.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	DEFAULT	Default capture
0x1	CAPTMIN	Minimum capture
0x2	CAPTMAX	Maximum capture
0x3	—	Reserved

Bits 25:24 – CAPTMODE0[1:0] Capture mode Channel 0

This bit field selects the channel 0 capture mode.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	DEFAULT	Default capture
0x1	CAPTMIN	Minimum capture
0x2	CAPTMAX	Maximum capture
0x3	—	Reserved

Bits 20, 21 – COPENn Capture On Pin n Enable

Bit n of COPEN[1:0] selects the trigger source for capture the operation, choosing between events or I/O pin input.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	An event from the Event System is selected as trigger source for capture operation on channel n
1	An I/O pin is selected as trigger source for the capture operation on channel n

Bits 16, 17 – CAPTENn Capture Channel n Enable

Bit n of CAPTEN[1:0] selects whether channel n operates as a capture or a compare channel.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	CAPTEN disables capture on channel n
1	CAPTEN enables capture on channel n

Bit 15 – DMAOS DMA One-Shot Trigger Mode

Writing a ‘1’ to this bit will generate the DMA trigger on a TC clock cycle following a TC_CTRLBSET_CMD_DMAOS command. Writing a ‘0’ to this bit will generate DMA triggers on every TC clock cycle.

Value	Description
0	Generate a DMA trigger on the TC clock cycle following a TC_CTRLBSET_CMD_DMAOS command
1	Generate DMA triggers on every TC clock cycle

Bit 11 – ALOCK Auto Lock

When this bit is set, the Lock bit update (LUPD) is set to ‘1’ on each overflow, underflow or retrigger event.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	The LUPD bit is not affected on overflow, underflow, and retrigger event
1	The LUPD bit is set on each overflow, underflow or retrigger event

Bits 10:8 – PRESCALER[2:0] Prescaler

This bit field selects the counter prescaler factor.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	DIV1	Prescaler: GCLK_TC
0x1	DIV2	Prescaler: GCLK_TC/2
0x2	DIV4	Prescaler: GCLK_TC/4
0x3	DIV8	Prescaler: GCLK_TC/8
0x4	DIV16	Prescaler: GCLK_TC/16
0x5	DIV64	Prescaler: GCLK_TC/64
0x6	DIV256	Prescaler: GCLK_TC/256
0x7	DIV1024	Prescaler: GCLK_TC/1024

Bit 7 – ONDEMAND Clock On Demand

This bit selects the clock requirements when the TC is stopped.

In Standby mode, if the Run in Standby bit (CTRLA.RUNSTDBY) is ‘0’, ONDEMAND is forced to ‘0’.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	On Demand is disabled. When On Demand is disabled, the TC will continue to request the clock even when its operation is stopped (STATUS.STOP=1).
1	On Demand is enabled. When On Demand is enabled, the stopped TC will not request the clock. The clock is requested only when a software retrigger command is issued or when an event with start or retrigger action is detected.

Bit 6 – RUNSTDBY Run in Standby

This bit is used to keep the TC running in Standby mode.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	The TC is halted in Standby
1	The TC continues to run in Standby

Bits 5:4 – PRESCSYNC[1:0] Prescaler and Counter Synchronization

This bit field controls whether the counter wraps around on the next GCLK_TCn clock or the next prescaled GCLK_TCn clock. It also allows the prescaler to be reset.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	GCLK	Reload or reset the counter on next generic clock
0x1	PRESC	Reload or reset the counter on next prescaler clock
0x2	RESYNC	Reload or reset the counter on next generic clock. Reset the prescaler counter.
Other	—	Reserved

Bits 3:2 – MODE[1:0] Timer Counter Mode

This bit field controls the counter mode.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	COUNT16	Counter in 16-bit mode
0x1	COUNT8	Counter in 8-bit mode
0x2	COUNT32	Counter in 32-bit mode
Other	—	Reserved

Bit 1 – ENABLE Enable

Note:

This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure that synchronization of CTRLA.ENABLE iscomplete.
This bit is not enable-protected.

Value	Description
0	The peripheral is disabled
1	The peripheral is enabled

Bit 0 – SWRST Software Reset

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be disabled.

Writing a ‘1’ to CTRLA.SWRST will always take precedence; all other writes in the same write operation will be discarded.

Note:

When CTRLA.SWRST is written, the user must poll the SYNCBUSY.SWRST bit to determine when the reset operation is complete.
During a SWRST operation, access to registers or bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.
This bit is not enable-protected.

Name:	CTRLA
Offset:	0x00
Reset:	0x00000000
Property:	PAC Write-Protection, Write-Synchronized, Enable-Protected