30.4.3.5 Hardware Controlled SS

In Host mode, an SPI Select (SS) line can be controlled by hardware by writing the Host SPI Select Enable (CTRLB.MSSEN) bit to ’1’. In this mode, the SS pin is driven low for at least one baud cycle before transmission begins, and stays low for at least one baud cycle after transmission completes. The SS pin will always be driven high for at least one baud cycle between each data sent.

In Figure 30-7, the time T ranges from one to two baud cycles depending on the SPI transfer mode.

When CTRLB.MSSEN is ‘0’, the SS pin(s) is/are controlled by user software and normal GPIO.