31.6.1 Control A

This bit enables the SCL low time-out. If SCL is held low for 25 ms–35 ms, the client will release its clock hold, if enabled, and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set.

This bit controls when SCL will be stretched for software interaction.

These bits define the bus speed.

This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25 ms from the initial START to a STOP, the client will release its clock hold if enabled and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set. If the address was recognized, PREC will be set when a STOP is received.

These bits define the SDA hold time with respect to the negative edge of SCL.

This bit sets the pin usage to either two- or four-wire operation:

This bit defines the functionality in Standby Sleep mode.

This bit field controls the SERCOM mode.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.

Writing ‘1’ to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register.