10.6.1 Synchronization Busy
| Name: | SYNCBUSY |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GENCTRL3 | GENCTRL2 | GENCTRL1 | GENCTRL0 | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 2, 3, 4, 5 – GENCTRLn Generator Control n Synchronization Busy
This bit is cleared when synchronization of the Generator Control n (GENCTRL[n]) register between clock domains is complete, or when a clock switching operation is complete.
This bit is set when the GENCTRL[n] register synchronization between clock domains is started.