10.6.2 Generator Control

The GENCTRL[n] register controls the settings of Generator n.

A Device Reset will reset all GENCTRL[n] registers. The Reset values of the GENCTRL[n] registers are shown in the Generic Clock After Reset section and are listed below:

Generator 0: 0x00000105
All other Generators: 0x00000000

Name:	GENCTRL[n]
Offset:	0x20 + n*0x04 [n=0..3]
Reset:	0x00000000
Property:	PAC Write-Protection, Write-Synchronized


Bit	31	30	29	28	27	26	25	24
	DIV[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
				SRC[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 31:16 – DIV[15:0] Division Factor

This bit field holds the division value for the corresponding Generator. The actual division factor used is dependent on the state of the Divide Selection bit (GENCTRL[n].DIVSEL). The number of relevant DIV bits for each Generator are shown in the table below. Bit values outside the specified range will be ignored.

Table 10-8. Division Factor Bits
Generic Clock Generator	Division Factor Bits
Generator 0	8 division factor bits - DIV[7:0]
Generator 1	16 division factor bits - DIV[15:0]
Generator 2	8 division factor bits - DIV[7:0]
Generator 3	8 division factor bits - DIV[7:0]

Bit 13 – RUNSTDBY Run in Standby

This bit is used to keep the Generator running in Standby sleep mode as long as it is configured to output to a dedicated GCLK_IO pin. If the Output Enable bit (GENCTRL[n].OE) is ‘0’, this bit has no effect, and the generator will only run if a peripheral requires the clock.

Value	Description
0	The Generator is stopped in Standby sleep mode, and the GCLK_IO pin state will depend on the value of the Output Off Value bit (GENCTRL[n].OOV)
1	The Generator is kept running, and the output is routed to its dedicated GCLK_IO pin when the device is in Standby sleep mode

Bit 12 – DIVSEL Divide Selection

This bit determines how the division factor of the clock source of the Generator will be calculated from DIV.

If the clock source should not be divided, DIVSEL must be set to ‘0’ and the GENCTRL[n].DIV value must be either ‘0x0’ or ‘0x1’.

Value	Name	Description
0	DIV1	The Generator clock frequency equals the clock source frequency divided by GENCTRL[n].DIV
1	DIV2	The Generator clock frequency equals the clock source frequency divided by 2^{(GENCTRL[n].DIV + 1)}

Bit 11 – OE Output Enable

This bit is used to output the generator clock to the corresponding pin (GCLK_IO[n]), as long as GCLK_IO is not selected as the generator source in the Generator Clock Source Selection bit field (GENCTRL[n].SRC).

Value	Description
0	No Generator clock signal on the GCLK_IO[n] pin
1	The Generator clock signal is output on the corresponding GCLK_IO[n] pin, unless GCLK_IO is selected as a generator source in the GENCTRL[n].SRC bit field

Bit 10 – OOV Output Off Value

This bit is used to control the clock output value on pin (GCLK_IO[n]) pin when the Generator is turned off or the OE bit is zero, as long as GCLK_IO is not defined as the Generator source in the GENCTRL[n].SRC bit field.

Value	Description
0	The GCLK_IO[n] pin will be LOW when the generator is turned off or when the OE bit is ‘`0`’
1	The GCLK_IO[n] pin will be HIGH when the generator is turned off or when the OE bit is ‘`0`’

Bit 9 – IDC Improve Duty Cycle

This bit is used to improve the duty cycle of the Generator output to 50/50 for odd division factors.

Note:

If DIVSEL = ‘1’, then IDC must always be set to ‘0’
If DIVSEL = ‘0’, then:
- If DIV is an odd number, IDC must be set to ‘1’
- If DIV is an even number, IDC must be set to ‘0’

Value	Description
0	The generator output clock duty cycle is not balanced to 50/50 for odd division factors
1	The generator output clock duty cycle is 50/50

Bit 8 – GENEN Generator Enable

This bit is used to enable and disable Generator n.

Note: For Generator 0, the reset value of this bit is ‘1’ since it is automatically enabled after a Device Reset. For all other generators, the reset value of this bit is ‘0’.

Value	Description
0	Generator n is disabled
1	Generator n is enabled

Bits 4:0 – SRC[4:0] Generator Clock Source Selection

These bits select the Generator clock source.

Value	Name	Description
0x00	OSCHF	OSCHF oscillator output
0x01	GCLKIN	Generator input pin (GCLK_IO)
0x02	GCLKGEN1	Generic Clock Generator 1 output
0x03	OSC32K	OSC32K oscillator output
0x04	XOSC32K	XOSC32K oscillator output
0x05-0x1F	Reserved	-