21.4.2.3 16-Bit Counter (Mode 1)

When the RTC Operating Mode bit field in the Control A register (CTRLA.MODE) is configured to COUNT16, the counter operates in 16-bit Counter mode, as shown in Figure 21-2. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit Period (PER) register holds the maximum value of the counter. The counter will increment until it reaches the PER value, and then wrap to ‘0x0000’. This sets the Overflow interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF).

The RTC counter value can be read from or written to the Counter Value (COUNT) register in 16-bit format. To read valid counter values, the COUNT register requires synchronization prior to reading. This is achieved by writing the COUNT Read Resynchronization Enable bit in the Control A register (CTRLA.COUNTSYNC) to ‘1’ and waiting for the COUNT Read Resynchronization Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.COUNTSYNC) to clear. Once enabled, the counter value is continuously resynchronized. Disabling the resynchronization will prevent reading valid values from the COUNT register.

The counter value is continuously compared with the 16-bit Compare n Value (COMP[n]) registers. When a compare match occurs, the corresponding Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next 0-to-1 transition of CLK_RTC_CNT.