21.4.2.4 Clock/Calendar (Mode 2)

When the RTC Operating Mode bit field in the Control A register (CTRLA.MODE) is configured to CLOCK, the counter operates in Clock/Calendar mode, as shown in Figure 21-3. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC prescaler must be configured to provide a 1 Hz clock to the counter for correct operation in this mode.

The time and date can be read from or written to the Clock Value (CLOCK) register in a 32-bit time and date format. To read valid clock values, the CLOCK register requires synchronization prior to reading. This is achieved by writing the CLOCK Read Resynchronization Enable bit in the Control A register (CTRLA.CLOCKSYNC) to ‘1’ and waiting for the CLOCK Read Resynchronization Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.CLOCKSYNC) to complete. Once enabled, the clock value is continuously resynchronized. Disabling the resynchronization will prevent valid values from being read from the CLOCK register.

Time is represented as:

• Seconds (0–59)
• Minutes (0–59)
• Hours

Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control A register (CTRLA.CLKREP). This bit can be changed only while the RTC is disabled. In 24-hour clock format, the Hour bit field in the CLOCK register (CLOCK.HOUR) can have values from 0 to 23. In 12-hour clock format, CLOCK.HOUR can have values from 1 to 12, while the Meridiem Indicator bit field (CLOCK.INDICATOR) indicates whether the clock value is before (AM) or after midday (PM).

The date is represented in the following form:

• Day as the numeric day of the month (starting at 1 and ending at 28–31, depending on the month and year)
• Month as the numeric month of the year (1 = January, 2 = February, …, 12 = December)
• Year as a value from ‘0x00’ to ‘0x3F’. This value must be added to a user-defined reference year. The reference year must be a leap year (2016, 2020 and so on). For example, the year value ‘0x2D’, when added to the reference year 2016, represents the year 2061.

The RTC will increment until it reaches the top value of 23:59:59 on December 31 of year value ‘0x3F’, and then wrap to 00:00:00 on January 1 of year value ‘0x00’. This will set the Overflow interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF).

The clock value is continuously compared with the 32-bit Alarm n Value (ALARMn) register. The time and date for the ALARMn register are defined similarly to those for the CLOCK register. When an alarm match occurs, the Alarm n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.ALARMn) is set on the next 0-to-1 transition of CLK_RTC_CNT. For example, with a 1 Hz clock counter, the Alarm n interrupt flag is set with a delay of 1 second after the occurrence of an alarm match.

A valid alarm match depends on the configuration of the Alarm n Mask Selection bit field in the Alarm n Mask register (MASKn.SEL). This bit field determines which time and date fields of the clock and alarm values are used for comparison and which are ignored.