21.4.2.2 32-Bit Counter (Mode 0)

When the RTC Operating Mode bit field in the Control A register (CTRLA.MODE) is configured to COUNT32, the counter operates in 32-bit Counter mode. The block diagram of this mode is shown in Figure 21-1. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of ‘0xFFFFFFFF’, and then wrap to ‘0x00000000’. This sets the Overflow interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF).

The RTC counter value can be read from or written to the Counter Value (COUNT) register in 32-bit format. To read valid counter values, the COUNT register requires synchronization prior to reading. This is achieved by writing the COUNT Read Resynchronization Enable bit in the Control A register (CTRLA.COUNTSYNC) to ‘1’ and waiting for the COUNT Read Resynchronization Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.COUNTSYNC) to clear. Once enabled, the counter value is continuously resynchronized. Disabling the resynchronization will prevent valid values from being read from the COUNT register.

The counter value is continuously compared with the 32-bit Compare n Value (COMP[n]) register. When a compare match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next 0-to-1 transition of CLK_RTC_CNT.