14.4.4 Sleep Mode Operation

A sleep mode is entered by executing the Wait For Interrupt (WFI) instruction. The Sleep Mode bit field in the Sleep Configuration (SLEEPCFG.SLEEPMODE) register selects the level of the sleep mode.

Note: There is a small latency between the store instruction and the actual writing of the SLEEPCFG register due to bus bridges. Software must verify that the SLEEPCFG register contains the desired value before executing the WFI instruction.

Table 14-2. Sleep Mode Entry and Exit
Mode	Mode Entry	Wake-Up Sources
IDLE	SLEEPCFG.SLEEPMODE = IDLE	Synchronous⁽²⁾, Asynchronous⁽¹⁾
STANDBY	SLEEPCFG.SLEEPMODE = STANDBY	Synchronous⁽³⁾, Asynchronous⁽¹⁾

Note:

Asynchronous: Interrupt is generated on GCLK generic clock, external clock, or an external event.
Synchronous: Interrupt is generated on the APB clock.
Synchronous interrupt: Only for peripherals configured to run in Standby sleep mode.

Note: The type of wake-up source (synchronous or asynchronous) is specified in the interrupt section of each peripheral.

The sleep modes (Idle, Standby) and their effect on clock activity and the regulator are described in the table and the sections below.

Table 14-3. Sleep Mode Overview
Mode	CPU Clock	AHB/APB Clocks	Main Clock	GCLK0 Clock	GCLK1 -->n Clocks	Clock Sources		Regulator
Mode	CPU Clock	AHB/APB Clocks	Main Clock	GCLK0 Clock	GCLK1 -->n Clocks	ONDEMAND = `0`	ONDEMAND = `1`	Regulator
IDLE	Stop	Run⁽¹⁾	Run	Run	Run/Stop⁽²⁾	Run	Run/Stop⁽³⁾	Main⁽⁸⁾
STANDBY	Stop	Stop⁽⁴⁾	Stop⁽⁴⁾	Stop if RUNSTDBY=`0`		Stop if RUNSTDBY=`0`		ULP⁽⁷⁾
STANDBY	Stop	Stop⁽⁴⁾	Stop⁽⁴⁾	Stop/Run if RUNSTDBY=`1`⁽⁵⁾		Run if RUNSTDBY=`1`	Stop/Run if RUNSTDBY=`1`⁽⁶⁾	ULP⁽⁷⁾

Note:

The AHB and APB clocks operate up to the MCLK, and are supplied only to the peripherals requesting them. The other peripherals, not requesting the clocks, are gated at MCLK output.
Each GCLK (GCLK1 to GCLKn) operates if at least one peripheral requests the associated generated clock. If no peripheral requests the clock, it is stopped.
The clock source remains active if at least one GCLK Generator requests it. If no GCLK Generator is requesting the clock, the source is stopped. It will automatically restart when a peripheral requests a clock from a GCLK that is supplied by this clock source.
The AHB and APB clocks are stopped unless requested by at least one peripheral, and in this case, only provided to this/these peripherals through GCLK0 and MCLK.
Each GCLK generator is stopped unless the clock it generates is requested by at least one peripheral.
Each Clock Source is stopped unless the clock it generates is requested by at least one GCLK Generator.
The regulator state can be programmed using the SUPC.VREG.RUNSTDBY bit.
If running on a slow clock (e.g., 32 kHz), the ULP regulator is used.