5.5.1.3 Watchdog Timer Configuration Fuse

The default value given in this fuse description is the factory-programmed value and must not be mistaken for the Reset value.

Name:	WDTCFG
Offset:	0x0010
Reset:	0xFFFFFFFF
Property:	R/W

The bit group values of this fuse are written to the corresponding bit groups of the Control A (CTRLA), Configuration (CONFIG), and Early Warning Control (EWCTRL) registers in the Watchdog Timer peripheral (WDT) at start-up.


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					EWOFFSET[3:0]
Access					R/W	R/W	R/W	R/W
Reset					1	1	1	1


Bit	15	14	13	12	11	10	9	8
	WINDOW[3:0]				PER[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1


Bit	7	6	5	4	3	2	1	0
					ALWAYSON	WEN	ENABLE
Access					R/W	R/W	R/W
Reset					1	1	1

Bits 19:16 – EWOFFSET[3:0] Early Warning Interrupt Time Offset Fuse

This bit field value is loaded into the Early Warning Interrupt Time Offset (EWOFFSET) bit field of the WDT.EWCTRL register during Reset. Refer to the WDT - Watchdog Timer section for further details.

Value	Name	Description
0x0	CYC8	8 clock cycles
0x1	CYC16	16 clock cycles
0x2	CYC32	32 clock cycles
0x3	CYC64	64 clock cycles
0x4	CYC128	128 clock cycles
0x5	CYC256	256 clock cycles
0x6	CYC512	512 clock cycles
0x7	CYC1024	1024 clock cycles
0x8	CYC2048	2048 clock cycles
0x9	CYC4096	4096 clock cycles
0xA	CYC8192	8192 clock cycles
0xB - 0xF	—	Reserved

Bits 15:12 – WINDOW[3:0] Window

This bit field value is loaded into the WINDOW bit field of the WDT.CONFIG register during Reset. Refer to the WDT - Watchdog Timer section for further details.

Value	Name	Description
0x0	CYC8	8 clock cycles
0x1	CYC16	16 clock cycles
0x2	CYC32	32 clock cycles
0x3	CYC64	64 clock cycles
0x4	CYC128	128 clock cycles
0x5	CYC256	256 clock cycles
0x6	CYC512	512 clock cycles
0x7	CYC1024	1024 clock cycles
0x8	CYC2048	2048 clock cycles
0x9	CYC4096	4096 clock cycles
0xA	CYC8192	8192 clock cycles
0xB	CYC16384	16384 clock cycles
Other	—	Reserved

Bits 11:8 – PER[3:0] Time-Out Period

This bit field value is loaded into the PER bit field of the Watchdog Configuration (WDT.CONFIG) register during Reset. Refer to the WDT - Watchdog Timer section for further details.

Value	Name	Description
0x0	CYC8	8 clock cycles
0x1	CYC16	16 clock cycles
0x2	CYC32	32 clock cycles
0x3	CYC64	64 clock cycles
0x4	CYC128	128 clock cycles
0x5	CYC256	256 clock cycles
0x6	CYC512	512 clock cycles
0x7	CYC1024	1024 clock cycles
0x8	CYC2048	2048 clock cycles
0x9	CYC4096	4096 clock cycles
0xA	CYC8192	8192 clock cycles
0xB	CYC16384	16384 clock cycles
Other	—	Reserved

Bit 3 – ALWAYSON Always On

This bit value is loaded into the ALWAYSON bit field of the WDT.CTRLA register during Reset. Refer to the WDT - Watchdog Timer section for further details.

Value	Description
0	The WDT can be enabled and disabled through the ENABLE bit
1	The WDT is enabled and can only be disabled by a Power-on Reset (POR)

Bit 2 – WEN Window Mode Enable

This bit value is loaded into the WEN bit field of the WDT.CTRLA register during Reset. Refer to the WDT - Watchdog Timer section for further details.

Value	Description
0	Window mode is disabled
1	Window mode is enabled

Bit 1 – ENABLE Enable

This bit value is loaded into the ENABLE bit in the WDT.CTRLA register during Reset. Refer to the WDT - Watchdog Timer section for further details.

Value	Description
0	The WDT is disabled
1	The WDT is enabled