32.5.3 Clocks

The CCL bus clock (CLK_CCL_APB) can be enabled and disabled in the Main Clock Controller. The default state of CLK_CCL_APB is specified in the Peripheral Clock Masking section in the MCLK – Main Clock Controller chapter.

A generic clock (GCLK_CCL) may be required to operate the CCL, depending on which features are used. This clock must be configured and enabled in the Generic Clock Controller before using input events, filter, edge detection, or sequential logic. For more information, refer to the GCLK – Generic Clock Controller chapter.