25.5.3 Clocks

The EIC bus clock (CLK_EIC_APB) can be enabled and disabled by the Main Clock Controller. The default state of CLK_EIC_APB can be found in the Peripheral Clock Masking section.

Some optional functions require a peripheral clock, which can be either a generic clock (GCLK_EIC, for wider frequency selection) or a 32.768 kHz clock (CLK_OSC32K). One of the clock sources must be configured and enabled before using the peripheral:
  • GCLK_EIC is configured and enabled in the Generic Clock Controller
  • CLK_OSC32K is provided by the internal 32.768 kHz (OSC32K) oscillator in the OSC32KCTRL module

Both GCLK_EIC and CLK_OSC32K are asynchronous to the user interface clock (CLK_EIC_APB). Due to this asynchronicity, writes to certain registers require synchronization between the clock domains.