22.8.7 Interrupt Flag Status and Clear


Bit	7	6	5	4	3	2	1	0
			MC1	MC0			ERR	OVF
Access			R/W	R/W			R/W	R/W
Reset			0	0			0	0

Bits 4, 5 – MCn Match or Capture Channel n

This flag is set on a comparison match, or when the corresponding CC[n] register contains a valid capture value. This flag will generate an interrupt request if the corresponding Match or Capture Channel n Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCn) is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the corresponding Match or Capture Channel n interrupt flag.

In capture operation, this flag is automatically cleared when CC[n] register is read.

Bit 1 – ERR Error Interrupt Flag

This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel n interrupt flag is set, in which case there is nowhere to store the new capture.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the Error Interrupt flag.

Bit 0 – OVF Overflow Interrupt Flag

This flag is set after an overflow condition occurs and will generate an interrupt request if INTENSET.OVF is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the Overflow Interrupt flag.

Name:	INTFLAG
Offset:	0x0A
Reset:	0x00
Property:	–