Prior to any read access, this
register must be manually read synchronized by writing to the Command bit in the
Control B Set register (CTRLBSET.CMD = READSYNC) and wait for the manual read
synchronization to finish (SYNCBUSY.CTRLB and CTRLBSET.CMD are
‘0’).
This register is write-synchronized. The COUNT Synchronization Busy bit in the
Synchronization Busy register (SYNCBUSY.COUNT) must be checked to ensure that the
COUNT register write synchronization is complete.
Name:
COUNT
Offset:
0x14
Reset:
0x00000000
Property:
PAC Write-Protection,
Write-Synchronized
Bit
31
30
29
28
27
26
25
24
COUNT[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
COUNT[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
COUNT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
COUNT[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – COUNT[31:0] Counter Value
This bit field contains
the current counter value.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
