32.4.3 Sleep Mode Operation

When using the GCLK_CCL internal clocking, writing a '1' to the Run In Standby (CTRLA.RUNSTDBY) bit in the Control A register will allow GCLK_CCL to remain enabled in Standby sleep mode.

If CTRLA.RUNSTDBY=0, the GCLK_CCL will be disabled in Standby sleep mode. If the filter, edge detector or sequential logic are enabled, the LUT output will be forced to zero in Standby mode. In all other cases, the TRUTH table decoder will continue to operate, and the LUT output will be updated accordingly.

For further information, refer to the PM - Power Manager chapter.