32.4.2.6 Sequential Logic

Each LUT pair can be connected to the internal sequential logic, which can be configured to operate as a D flip-flop, JK flip-flop, gated D latch, or RS latch by configuring the Sequential Selection bits in the corresponding Sequential Control (SEQCTRL) register. Before using sequential logic, the GCLK_CCL clock must be enabled, and, if required, each LUT filter or edge detector should also be enabled.

Gated D Flip-Flop (DFF)

When D flip-flop (DFF) mode is selected, the D input is driven by the even LUT output (LUT0 or LUT2), and the G input is driven by the odd LUT output (LUT1 or LUT3), as illustrated in the figure below.

The flip-flop output (OUT) is updated on the rising edge of the GCLK_CCL, as shown in the table below.

JK Flip-Flop (JK)

When this configuration is selected, the J input is driven by the even LUT output (LUT0 or LUT2), and the K input is driven by the odd LUT output (LUT1 or LUT3), as illustrated in the figure below.

The flip-flop output (OUT) is updated on the rising edge of GCLK_CCL, as shown in the table below.

Gated D Latch (DLATCH)

When DLATCH is selected, the D input is driven by the even LUT output (LUT0 or LUT2), and the G input is driven by the odd LUT output (LUT1 or LUT3), as illustrated in the figure below.

The latch output (OUT) is updated as shown in the table below.

RS Latch (RS)

When this configuration is selected, the S input is driven by the even LUT output (LUT0 or LUT2), and the R input is driven by the odd LUT output (LUT1 or LUT3), as illustrated in the figure below.

The latch output (OUT) is updated as shown in the table below.