2.1 Basic Operation

Initialization

The SDADC must be configured with the peripheral disabled. The register setting sequence to configure and enable the SDADC is as follows where the notations are stated in the form <register.bit(s)>:

  • Enable the Generic Clock
  • Select the Voltage Reference and Range
    • REFCTRL.REFRANGE
    • REFCTRL.REFSEL
  • Set the Conversion Rate and Resolution
    • GCLK_SDADC
    • CTRLB.PRESCALER (SDADC_CLK)
    • CTRLB.OSR (Over Sampling Ratio)
  • Select trigger source or interrupts
    • SWTRIG.START (Software Trigger)
    • Free Run Mode
    • DMA/Event
    • Timers
  • Sequence Control
    • Automatic Sequences (SEQCTRL)
    • Lower-to-Upper Positive Pairs
    • The SEQSTATUS.SEQBUSY bit will be set when a conversion is initiated and cleared when sequence is complete
    • The input number is stored with the RESULT
  • Window Monitor Control
    • RESULT compared to threshold
    • WINUT/WINLT (Upper and Lower Thresholds)
    • WINCTRL.WINMODE (Inside/Outside window)
    • INTFLAG.WINMON (Interrupt flag)
  • Configure Input Pins
    • INPUTCTRL.MUXSEL[3:0]
  • Configure Interrupts
    • INTENSET.RESRDY (Conversion ready)
    • INTENSET.WINMON (Threshold reached)
    • INTENSET.OVERRUN (previous result not read)

Reading the Results

The SDADC result ready flag (RESRDY) will be set when a conversion is complete. When the peripheral is first initialized, the results are only valid after the 3rd conversion. To automate this limitation in hardware, the register set includes the skip count field in the CTRLB register (CTRLB.SKPCNT[3:0]) to automatically skip the first ‘n’ results. When in free running mode, the application must read the result prior to the next result being ready. If this does not happen, the overrun flag will be set.

The result is read from the RESULT register.