7.3.2 I2C Interface Timing
Parameters | Symbol | Fast-Mode Plus | Units | |
---|---|---|---|---|
Min. | Max. | |||
SCL Clock Frequency | fSCL | — | 1000 | kHz |
SCL High Time | tHIGH | 260 | — | ns |
SCL Low Time | tLOW | 500 | — | ns |
Start Setup Time | tSU.STA | 260 | — | ns |
Start Hold Time | tHD.STA | 260 | — | ns |
Stop Setup Time | tSU.STO | 260 | — | ns |
Data in Setup Time | tSU.DAT | 50 | — | ns |
Data in Hold Time | tHD.DAT | 0 | — | ns |
Input Rise Time(1, 3) | tR | — | 120 | ns |
Input Fall Time(1, 3) | tF | 20 x (VDD/5.5V)(5) | 120 | ns |
Clock Low to Data Out Valid | tAA | — | 450 | ns |
Time bus must be free before a new transmission can start (1) | tBUF | 500 | — | ns |
Pulse width of spikes that must be suppressed by the input filter(4) | tSP | — | 50 | ns |
Note:
- Values are based on characterization and are not tested.
- AC measurement conditions: input pulse voltages: 0.3 x VCC to 0.7 x VCC, input rise and fall times: ≤ 50 ns.
- System designers must ensure that all AC parametrics are met. Rise fall times shown are for the Fast Mode Plus (1 MHz) of operation. For slower clock speeds, the rise and fall times may be increased but must still meet the industry standard I2C specification UM10204.
- Input filters on the SDA and SCL pins will suppress noise spikes of less than 50 ns.
- Backwards compatibility is necessary for the Fast mode (400 kHz) specifications.