3.2 DC/AC Characteristics

**Electrical Specifications:** Unless otherwise noted, V_IN = V_R + 1V (Note 1), I_OUT = 1 mA, C_IN = C_OUT = 3.3 µF ceramic (X7R), T_J = +25°C, SHDN > 2.4V. **Boldface** type applies for junction temperatures T_J of –40°C to +150°C (Note 2).
Parameters	Sym.	Min.	Typ.	Max.	Units	Conditions
DC Performance
Input Operating Voltage	V_IN	4.3	—	55	V	V_OUT = 3.3V
6	—	55	V	V_OUT = 5.0V
4	—	55	V	V_OUT = Adjustable (ADJ)
ADJ Nominal Reference Value	V_REF	1.18	1.21	1.24	V	Adjustable output version
ADJ Leakage Current	I_ADJ(LKG)	—	—	100	nA	Adjustable output version
Output Voltage Accuracy	V_OUT	V_R – 2%	V_R	V_R + 2%	%	Fixed output versions
V_R – 3%	V_R	V_R + 3%	Adjustable output version. Assumes perfect external divider.
Input Quiescent Current	I_Q	—	34	57	µA	V_IN(MIN)≤ V_IN ≤55V; I_OUT = 0 mA
Input Quiescent Current for SHDN Mode	I_SHDN	—	3.5	15	µA	SHDN = GND, V_IN = 55V
Ground Current	I_GND	—	85	122	µA	I_GND = I_IN – I_OUT I_OUT = 200 mA
Maximum Output Current	I_OUT	200	—	—	mA	(Note 2)
Line Regulation	Δ_VOUT/ (V_OUTxΔV_IN)	-0.005	±0.002	+0.005	%/V	V_IN(MIN) ≤ V_IN ≤55V
Load Regulation	ΔV_OUT/V_OUT	-0.1	±0.06	+0.1	%	I_OUT =1 mA to 200 mA
Dropout Voltage	V_DROPOUT	—	380	705	mV	I_OUT =200 mA (Note 3)
AC Performance
Output Noise	e_N	—	300	—	µVrms	f = 10 Hz to 10 MHz, V_IN = 16V, I_OUT = 100 mA (Note 5)
Power Supply Rejection Ratio	PSRR	—	–80	—	dB	f = 100 Hz (Note 4) (Note 5)
—	–65	—	f = 1 kHz (Note 4) (Note 5)
—	–36	—	f = 100 kHz (Note 4) (Note 5)
Current Limit
Foldback Current Limit	I_CL	—	450	—	mA	(Note 5)
Foldback Current	I_FOLDBACK	—	10	—	mA	V_OUT ≈ 0V (Note 5)
Undervoltage Lock Out
Input Voltage to Turn-on Output	V_UVLO(HI)	—	2.7	—	V	Rising V_IN
Input Voltage to Turn-off Output	V_UVLO(LO)	—	2.3	—	V	Falling V_IN
Shutdown
Logic High Input	V_{SHDN (HI)}	1.13	—	—	V
Logic Low Input	V_{SHDN (LO)}	—	—	0.79	V
SHDN Input Leakage Current	I_SHDN(LK)	—	—	0.22	µA	V_SHDN = 55V
Turn-off delay	t_SHDN(OFF)	—	22	—	µs	V_SHDN Falling (Note 5)
Soft Start
Soft Start Timing	t_ss	—	450	720	µs	From 10% of V_R to 90% of V_R
Start-up Delay	t_DELAY	—	600	—	μs	From V_IN = V_SHDN = 0V to VR + 1V, until V_OUT = 10% of V_R (See Note 5)
Power Good
Power Good Threshold	V_PWG(TH)	90	94	97	% VOUT	Rising V_OUT
Power Good Hysteresis	V_PWG(HYS)	1	3	6	% VOUT	Falling V_OUT
Power Good Sink Capability	I_PWG(SINK)	5	—	—	mA
Power Good Output Voltage Low	V_PWG(VOL)	—	36	66	mV	I_PWGSINK = 5 mA; V_OUT = 0V
Power Good Leakage	I_PWG(LKG)	—	—	20	nA	V_PWG = 5.5V
Power Good Delay Rising	t_PWG(RISE)	—	98	—	µs	Delay after V_OUT crosses Power Good Threshold (Note 5)
Power Good Delay Falling	t_PWG(FALL)	—	105	—	µs	Delay after V_OUT crosses Power Good Threshold minus Hysteresis (Note 5)
Output Discharge Transistor
Discharge Resistance	R_DS(ON)	—	105	—	Ω	(Note 5)
Notes: VR is the nominal output voltage. The minimum input voltage is 4.3V for V_R = 3.3V and 6V for V_R = 5V. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., T_A, T_J, θ_JA). See the Temperature Specifications table and Section 5. Application Information. Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained junction temperatures above 150°C can impact the device reliability. Dropout voltage is defined as the input to output voltage differential at which the output voltage drops 2% below its nominal value. PSRR measurement is carried out with C_IN =0 µF, V_IN = 14.5V, I_OUT = 100 mA, V_INAC = 0.4 V_pkpk. Not production tested.

DC Performance

Input Operating Voltage

V_IN

4.3

—

55

V

V_OUT = 3.3V

6

—

55

V

V_OUT = 5.0V

4

—

55

V

V_OUT = Adjustable (ADJ)

ADJ Nominal Reference Value

V_REF

1.18

1.21

1.24

V

Adjustable output version

ADJ Leakage Current

I_ADJ(LKG)

—

100

nA

Adjustable output version

Output Voltage Accuracy

V_OUT

V_R – 2%

V_R

V_R + 2%

%

Fixed output versions

V_R – 3%

V_R

V_R + 3%

Adjustable output version. Assumes perfect external divider.

Input Quiescent Current

I_Q

—

34

57

µA

V_IN(MIN)≤ V_IN ≤55V; I_OUT = 0 mA

Input Quiescent Current for SHDN Mode

I_SHDN

—

3.5

15

µA

SHDN = GND, V_IN = 55V

Ground Current

I_GND

—

85

122

µA

I_GND = I_IN – I_OUT

I_OUT = 200 mA

Maximum Output Current

I_OUT

200

—

mA

(Note 2)

Line Regulation

Δ_VOUT/

(V_OUTxΔV_IN)

-0.005

±0.002

+0.005

%/V

V_IN(MIN) ≤ V_IN ≤55V

Load Regulation

ΔV_OUT/V_OUT

-0.1

±0.06

+0.1

%

I_OUT =1 mA to 200 mA

Dropout Voltage

V_DROPOUT

—

380

705

mV

I_OUT =200 mA (Note 3)

AC Performance

Output Noise

e_N

—

300

—

µVrms

f = 10 Hz to 10 MHz,

V_IN = 16V, I_OUT = 100 mA

(Note 5)

Power Supply Rejection Ratio

PSRR

—

–80

—

dB

f = 100 Hz

(Note 4) (Note 5)

—

–65

—

f = 1 kHz

(Note 4) (Note 5)

—

–36

—

f = 100 kHz

(Note 4) (Note 5)

Current Limit

Foldback Current Limit

I_CL

—

450

—

mA

(Note 5)

Foldback Current

I_FOLDBACK

—

10

—

mA

V_OUT ≈ 0V (Note 5)

Undervoltage Lock Out

Input Voltage to Turn-on Output

V_UVLO(HI)

—

2.7

—

V

Rising V_IN

Input Voltage to Turn-off Output

V_UVLO(LO)

—

2.3

—

V

Falling V_IN

Shutdown

Logic High Input

V_{SHDN
(HI)}

1.13

—

V

Logic Low Input

V_{SHDN
(LO)}

—

0.79

V

SHDN Input Leakage Current

I_SHDN(LK)

—

0.22

µA

V_SHDN = 55V

Turn-off delay

t_SHDN(OFF)

—

22

—

µs

V_SHDN Falling (Note 5)

Soft Start

Soft Start Timing

t_ss

—

450

720

µs

From 10% of V_R to 90% of V_R

Start-up Delay

t_DELAY

—

600

—

μs

From V_IN = V_SHDN = 0V to VR + 1V, until V_OUT = 10% of V_R (See Note 5)

Power Good

Power Good Threshold

V_PWG(TH)

90

94

97

% VOUT

Rising V_OUT

Power Good Hysteresis

V_PWG(HYS)

1

3

6

% VOUT

Falling V_OUT

Power Good Sink Capability

I_PWG(SINK)

5

—

mA

Power Good Output Voltage Low

V_PWG(VOL)

—

36

66

mV

I_PWGSINK = 5 mA; V_OUT = 0V

Power Good Leakage

I_PWG(LKG)

—

20

nA

V_PWG = 5.5V

Power Good Delay Rising

t_PWG(RISE)

—

98

—

µs

Delay after V_OUT crosses Power Good Threshold (Note 5)

Power Good Delay Falling

t_PWG(FALL)

—

105

—

µs

Delay after V_OUT crosses Power Good Threshold minus Hysteresis (Note 5)

Output Discharge Transistor

Discharge Resistance

R_DS(ON)

—

105

—

Ω

(Note 5)

Notes:

VR is the nominal output voltage. The minimum input voltage is 4.3V for V_R = 3.3V and 6V for V_R = 5V.
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., T_A, T_J, θ_JA). See the Temperature Specifications table and Section 5. Application Information. Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained junction temperatures above 150°C can impact the device reliability.
Dropout voltage is defined as the input to output voltage differential at which the output voltage drops 2% below its nominal value.
PSRR measurement is carried out with C_IN =0 µF, V_IN = 14.5V, I_OUT = 100 mA, V_INAC = 0.4 V_pkpk.
Not production tested.