18.4.12 APMCLK

Analog Peripheral Manager Clock Selection Register

Name:	APMCLK
Address:	0x1D8


Bit	7	6	5	4	3	2	1	0
							CLK[1:0]
Access							R/W	R/W
Reset							0	0

Bits 1:0 – CLK[1:0] Analog Peripheral Manager Clock Selection

Table 18-2. Analog Peripheral Manager Module Clock Sources
CLK [1:0]	APM Clock Source
`11`	ADCRC
`10`	SOSC
`01`	LFINTOSC
`00`	Pin selected by APMCLKPPS

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