23.11.8 Asynchronous Status Register
Name: | ASSR |
Offset: | 0xB6 |
Reset: | 0x00 |
Property: | - |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
EXCLK | AS2 | TCN2UB | OCR2AUB | OCR2BUB | TCR2AUB | TCR2BUB | |||
Access | R/W | R/W | R | R | R | R | R | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 6 – EXCLK Enable External Clock Input
Bit 5 – AS2 Asynchronous Timer/Counter2
Bit 4 – TCN2UB Timer/Counter2 Update Busy
Bit 3 – OCR2AUB Output Compare Register2A Update Busy
Bit 2 – OCR2BUB Output Compare Register2B Update Busy
Bit 1 – TCR2AUB Timer/Counter Control Register2 Update Busy
Bit 0 – TCR2BUB Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value.
If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur.