50.9.3 Sleep Mode Current Consumption

Sleep mode configuration and measurements are defined in this section.

Remember: In Sleep mode, power consumption of the device is optimized with respect to response time.
  • VDD3V3 = 3.3V
  • VDDCORE/VDDPLL = Internal Voltage regulator used
  • TA = 25°C
  • Core 0 clock (CPU_CLK0) and Core 1 (CPU_CLK1) clock stopped
  • Sub-system 0 Main Clock (MCK0, MCK0DIV,MCK0DIV2), Sub-system 1 Main Clock (MCK1, MCK1DIV) in Sleep mode at various frequencies.
  • All peripheral clocks deactivated
  • No activity on I/O lines
  • Current measurement as illustrated in the figure below
Figure 50-29. Measurement Setup for Sleep Mode
Table 50-61. Sleep Mode Current Consumption Versus Frequency
Cores Clock / Main Clock (MHz)AMP1AMP2Unit
Core 0 Clock/Main Clock 
MCK0, MCK0DIV, MCK0DIV2Core 1 Clock/Main Clock 
MCK1, MCK1DIV
200/200, 100, 200240/240, 1203523mA
100/100, 100, 100120/120, 12028.516.5mA
50/50, 50, 5060/60, 602412mA