16.5.2 RSTC Status Register
| Name: | RSTC_SR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SRCMP | NRSTL | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RSTTYP[3:0] | |||||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CORESMS | URSTS | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 17 – SRCMP Software Reset Command in Progress
When set, this bit indicates that a Software reset command is in progress and that no further Software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current Software reset.
| Value | Description |
|---|---|
| 0 | No Software reset command is being performed by the RSTC. The RSTC is ready for a Software reset command. |
| 1 | A Software reset command is being performed by the RSTC. |
Bit 16 – NRSTL NRST Pin Level
Reports NRST pin level after sampling on MCK clock.
Bits 11:8 – RSTTYP[3:0] Reset Type
Reports the cause of the last processor reset. Reading RSTC_SR does not reset this field.
Values not listed below must be considered ‘reserved’.
| Value | Name | Description |
|---|---|---|
| 0 | GENERAL_RST | First power-up reset, Core and VDD3V3 Supply Monitor if not a PORVDD3V3 reset |
| 1 | BACKUP_RST | VDDCORE reset. Wake-up from Backup mode. |
| 2 | WDT0_RST | Watchdog 0 fault occurred |
| 3 | SOFT_RST | Processor reset required by the software |
| 4 | USER_RST | NRST pin detected low |
| 5 | CORE_SM_RST |
Core Supply Monitor reset |
| 6 | CPU_FAIL_RST | CPU clock failure detection occurred |
| 7 | SLCK_XTAL_RST | 32.768 kHz crystal failure detection fault occurred |
| 9 | WDT1_RST | Watchdog 1 fault occurred |
| 10 | PORVDD3V3_RST |
VDD3V3 (PORVDD3V3) reset occurred |
Bit 1 – CORESMS VDDCORE Supply Monitor Reset Flag Status (cleared on read)
| Value | Description |
|---|---|
| 0 |
No VDDCORE reset occurred since the last read of RSTC_SR. |
| 1 |
VDDCORE reset occurred since the last read of RSTC_SR. |
Bit 0 – URSTS User Reset Status (cleared on read)
Set when a high-to-low transition of the NRST pin (reset assertion) occurs. This transition is also detected on the MCK rising edge. If the User reset is disabled (URSTEN = 0 in RSTC_MR) and if the interrupt is enabled by RSTC_MR.URSTIEN, URSTS triggers an interrupt. Reading the RSTC_SR resets URSTS and clears the interrupt.
| Value | Description |
|---|---|
| 0 | No high-to-low edge on NRST pin happened since the last read of RSTC_SR. |
| 1 | At least one high-to-low transition of NRST pin has been detected since the last read of RSTC_SR. |