16.5.3 RSTC Mode Register

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).

Name:	RSTC_MR
Offset:	0x08
Reset:	0x000000F5
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	KEY[7:0]
Access	W	W	W	W	W	W	W	W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
		BADXTRST	PWRSW			CPROCEN	CPEREN	CORSMIEN
Access		R/W	R/W			R/W	R/W	R/W
Reset		0	0			0	0	0


Bit	15	14	13	12	11	10	9	8
					ERSTL[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	WDTPMC1	WDTPMC0	SFTPMCRS	URSTIEN	CPUFEN	URSTASYNC	SCKSW	URSTEN
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	0	1	0	1

Bits 31:24 – KEY[7:0] Write Access Password

Value	Name	Description
0xA5	PASSWD	Writing any other value in this field aborts the write operation. Always reads as 0.

Value

Name

Description

0xA5

PASSWD

Writing any other value in this field aborts the write operation.

Always reads as 0.

Bit 22 – BADXTRST Bad XTAL Fail Reset

Value	Description
0	The detection of a 32.768 kHz crystal failure has no effect.
1	The detection of a 32.768 kHz crystal failure resets the logic supplied by VDDCORE.

Bit 21 – PWRSW Backup Area Power Switch Control

Value	Description
0	VDDBU is supplied by VDD3V3.
1	VDDBU is supplied by VBAT.

Bit 18 – CPROCEN Coprocessor (Second Processor) Enable

Value	Description
0	If KEY = 0xA5, resets the coprocessor (power-on default value).
1	If KEY = 0xA5, deasserts the reset of the coprocessor.

Bit 17 – CPEREN Coprocessor Peripheral Enable

Value	Description
0	If KEY = 0xA5, resets the coprocessor peripherals.
1	If KEY = 0xA5, deasserts the reset of the coprocessor peripherals.

Bit 16 – CORSMIEN VDDCORE Supply Monitor Interrupt Enable

Value	Description
0	Disables VDDCORE supply monitor event interrupt.
1	Enables VDDCORE supply monitor event interrupt.

Bits 11:8 – ERSTL[3:0] External Reset Length

This field defines the external reset length. The external reset is asserted during a time of 2^(ERSTL+1) MD_SLCK cycles. This allows assertion duration to be programmed between 60 μs and 2 seconds. Note that synchronization cycles must also be considered when calculating the actual reset length as previously described.

Bit 7 – WDTPMC1 WDT1 PMC Reset

Value	Description
0	In case of a WDT1 reset, the PMC is not reset.
1	In case of a WDT1 reset, the PMC is reset.

Bit 6 – WDTPMC0 WDT0 PMC Reset

Value	Description
0	In case of a WDT0 reset, the PMC is not reset.
1	In case of a WDT0 reset, the PMC is reset.

Bit 5 – SFTPMCRS Software PMC Reset

Value	Description
0	In case of a Software reset, the PMC is not reset.
1	In case of a Software reset, the PMC is reset.

Bit 4 – URSTIEN User Reset Interrupt Enable

Value	Description
0	If RSTC_SR.USRTS =1 , no effect on the RSTC interrupt line.
1	If RSTC_SR.USRTS =1, asserts the RSTC interrupt line if URSTEN = 0.

Bit 3 – CPUFEN CPU Fail Enable

Value	Description
0	The detection of a CPU clock failure has no effect.
1	The detection of a CPU clock failure resets the logic supplied by VDDCORE.

Bit 2 – URSTASYNC User Reset Asynchronous Control

Value	Description
0	NRST input signal is managed synchronously.
1	NRST input signal is managed asynchronously.

Bit 1 – SCKSW Slow Clock Switching

Value	Description
0	The detection of a 32.768 kHz crystal failure has no effect.
1	The detection of a 32.768 kHz crystal failure automatically switches the TD_SLCK clock source to the slow RC oscillator.

Bit 0 – URSTEN User Reset Enable

Value	Description
0	The detection of a low level on the NRST pin does not trigger a User reset.
1	The detection of a low level on the NRST pin triggers a User reset.