8.1.1 Internal SRAM

The device embeds high-speed SRAM with zero wait state access time.

• SRAM0 is up to 512 Kbytes. It is dedicated to the Application Core and/or peripherals.
• SRAM1 is 32 Kbytes. It is dedicated to be the code region of the Metrology Core.
• SRAM2 is 16 Kbytes. It is dedicated to be the data region of the Metrology Core and/or peripherals.

The multibank and multiport RAM architecture provides an efficient way to optimize the access latency to the memory, whatever types of access are performed by the hosts.

A maximum of one system bus clock cycle is required to complete an access to the RAM. The predictability is therefore optimal.